For more than thirty years, the trend in the semiconductor industry has been to replace analogue circuitry with digital circuitry. Since the real world is analogue, this trend can never fully eliminate the conversion circuitry required to take real-world signals in and out of the digital domain. Most new chips being designed are now so-called mixed signal chips. These have mainly digital components, but a substantial number of converters (ADCs and DACs) are required.
During manufacturing each chip must be checked against a specification. The tests for converters are disproportionately expensive in relation to their size on the chip compared with the rest of the chip circuitry which is digital. At present, most tests are done using external test equipment with physical test-heads that are brought into contact with the circuit to allow a test to be conducted. Usually access to test the chip is restricted to pads around the chip edges. Access is getting harder because more, smaller functional blocks on the same size of chip must be tested. Physical test-heads have not kept up the rate of shrinkage that transistors have experienced. Built-in self-test (BIST) for analogue circuits is recognised as a viable way forward, but no commercial solution has yet emerged.
Received wisdom in the semiconductor industry demands that test circuit performance be higher specification than the circuit under test (CUT). Since CUTs typically push the limits of achievable performance, this apparently precludes creating a better test circuit on-chip. EP 11250312.3 describes a technique that shows the general barrier can be circumvented by splitting up the parameters to be tested. In this way, only narrow aspects of the test circuitry are required to be better than the corresponding aspect of the circuit under test. The highest performance is not required simultaneously across all the tested parameters. Thus, performance of the test circuit can be focussed on target aspects, so the task is now achievable.
For example, for the testing of very high fidelity audio output devices (DACs), received wisdom states that an ADC of higher performance must be used to measure the output and conventional signal processing requiring significant computing capability must be deployed. This is impracticable for a compact on-chip solution. Typically, for testing an audio DAC, it is set to output a fixed amplitude sine wave (for example 1 kHz) that is accurately monitored. A Fourier transform to the frequency domain is applied to detect any harmonic distortion. System-on-chip circuit designs tend to have more difficult challenges associated with analogue sections than with digital sections.
U.S. Pat. No. 7,026,966 describes a BIST for a DAC. The DAC output is held steady at a chosen code Ca and sampled on to a capacitor (as Va). Next the DAC is set to another code Cb and held steady. The DAC output and Va are connected to the inputs of a comparator, such that when the DAC input is changed back to Ca the output rises towards Va, tripping the comparator. The time for the DAC output to get back to Va is measured. This time measure is used to estimate the voltage step that the DAC output. This type of test is known as a static test and does not test essential dynamic behaviour compulsory to check audio and similar devices.
U.S. Pat. No. 7,773,011 describes a BIST for a resistor ladder DAC. The BIST relies on an externally generated analogue test voltage and compares it with the DAC output voltage to provide a digital pass/fail. This is carried out in a test mode where the resistor ladder in the DAC is connected through the test circuit in such a way as to allow testing of the individual resistors. A disadvantage of this arrangement is that an external voltage must be generated and so it still requires analog inputs from a tester. Also, the circuit described can test only static characteristics. A further disadvantage is that the test circuit is integrated as a part of the DAC. It is not a separate and independent test structure.